The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to embodiments of the claimed subject matter.
Today's consumer electronics market frequently demands complex functions requiring very intricate circuitry. Scaling to smaller and smaller fundamental building blocks, (e.g. transistors), has enabled the incorporation of even more intricate circuitry on a single die with each progressive generation. Semiconductor packages are used for protecting an integrated circuit (IC) chip or die, and also to provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic devices, semiconductor packages are designed to be even more compact and must support increased circuit density. Furthermore, the demand for higher performance devices results semiconductor and substrate packages which generate significant amounts of heat due to the package density and the high power devices integrated within such packages.
A key challenge with the manufacture of three-dimensional (3D) integrated circuit (IC) semiconductor packaging is to provide a design with sufficient heat dissipation properties from logic devices or other functional silicon devices embedded within the 3D package which generate heat and create hot spots internal to the 3D substrate package. The problem is especially problematic with 3D or stacked substrate packages because unlike conventional package substrates where such functional silicon dies are exposed at a top surface and may therefore be interfaced directly to a heat sink to collect and dissipate the heat, 3D or stacked packages may have one or more heat generating functional silicon dies buried or covered by one or more other silicon die due to the stacked silicon die formation.
Conventional solutions utilize a polymer dissipation means of heat dissipation for 3D packages or stacked die combinations. Heat is generated by, for instance, a logic device buried within the 3D package and prior solutions are not sufficiently effective at extracting the heat generated from the interior of the 3D package and transferring the heat to the surface where it may then be dissipated via for instance, an external heat sink.
The present state of the art may therefore benefit from the thermal solution for 3D packaging as is described herein.